Improving Verification through Property Specification

Silicon transistor capacity, the ability to utilize these transistors in a design, and the time required to verify these designs are all considerations that drive our decisions about architecting the next generation system-on-a-chip. While silicon capacity continues to increase along the Moore's Law curve (enabling us to create very large systems), the effort required to verify these larger designs has increased at an even greater, and thus alarming, rate-doubling roughly every 6 months. In addition to rising silicon capacity, our ability to utilize this larger silicon capacity has also increased approximately ten-fold within the past decade due to the widespread acceptance of synthesis technology. However, the ability to verify larger systems has not kept pace. Rather, verification productivity has experienced only incremental improvements during the same period. What is clearly needed in verification techniques and technology is the equivalent of a synthesis productivity break-though. This article explores a verification break-through prompted by multi-level specification techniques.