Do Standardized Embedded IP Transistor Views Exist for SoC IP Integration?

by Pierre Bricaud, Thomas Delaye, Franck Poirot and Adrian

The known roadblocks, power consumption-data management-multiOS-verification, to System-on-Chip development are being lifted by numerous creative solutions. One of these solutions is the availability of IP designs representations from architectural abstraction to transistors. The levels of IP abstraction or different levels of IP abstractions you make available to the system architect, designer, verifier, IP integrator and chip manufacturer will be paramount in the success of the design and verification process and especially from a time-to-market and cost aspect. We will describe how the choice of your system verification environment needs to span over multiple system application environments and especially applications or silicon technology migration where the accurate design representation of a crucial IP block has its golden representation as a transistor netlist which is the only design representation that allows fast technology migration for special silicon processes like low power CMOS, analog or memories. We will describe the abstraction techniques used to create the RTL view of the optimised transistor netlist to new silicon process in order to be used on the verification platform.

The last part of the paper will describe step by step the process from the SoC specifications' first mapping on the system verification environment of a 3G-radio sub-system, the transistor level optimisation of a specific memory controller block and final mapping and system verification with the new RTL view.