Using statistical activity for power estimation
Ashutosh Mauskar and Steev Wilcox, Azuro, Inc.
(07/24/2006 9:00 AM EDT), EE Times
Today, power is rapidly replacing performance as the primary concern for many digital chip design teams. Currently, the majority of 90nm design teams perform concurrent analysis and optimization for power, timing and signal integrity at multiple points in their design flow from architecture to routing.
Power, among other things, is a function of operating voltage, switching capacitance, and switching activity (dynamic power = ½CV2f). Standards for capturing operating voltage and switching capacitance are well established in design flows today, but the methodology for capturing the correct switching activities is currently more of an art than a science.
(07/24/2006 9:00 AM EDT), EE Times
Today, power is rapidly replacing performance as the primary concern for many digital chip design teams. Currently, the majority of 90nm design teams perform concurrent analysis and optimization for power, timing and signal integrity at multiple points in their design flow from architecture to routing.
Power, among other things, is a function of operating voltage, switching capacitance, and switching activity (dynamic power = ½CV2f). Standards for capturing operating voltage and switching capacitance are well established in design flows today, but the methodology for capturing the correct switching activities is currently more of an art than a science.
To read the full article, click here
Related Semiconductor IP
- ReRAM NVM in DB HiTek 130nm BCD
- UFS 5.0 Host Controller IP
- PDM Receiver/PDM-to-PCM Converter
- Voltage and Temperature Sensor with integrated ADC - GlobalFoundries® 22FDX®
- 8MHz / 40MHz Pierce Oscillator - X-FAB XT018-0.18µm
Related Articles
- Towards Activity Based System Level Power Estimation
- Speeding power estimation from weeks to hours
- Accurate and Efficient Power estimation Flow For Complex SoCs
- Unified Methodology for Effective Correlation of SoC Power Estimation and Signoff
Latest Articles
- An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks
- Enabling RISC-V Vector Code Generation in MLIR through Custom xDSL Lowerings
- A Scalable Open-Source QEC System with Sub-Microsecond Decoding-Feedback Latency
- SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks
- An FPGA Implementation of Displacement Vector Search for Intra Pattern Copy in JPEG XS