Speeding power estimation from weeks to hours

Ophir Turbovich, Cambridge Silicon Radio and Thomas Li, SpringSoft
EETimes (11/19/2012 10:59 AM EST)

This paper describes a new methodology that automatically generates a chip design’s gate-level waveform from the RTL design environment without the need to bring up the gate-level environment. The new waveform generation methodology reduces the effort to perform gate-level power estimation from weeks to hours, using established EDA technology from Springsoft  and Cambridge Silicon Radio's established power estimation flow and tools. This major reduction in effort and increase in designer productivity enables CSR to analyze power characteristics much earlier in the design flow than is practically possible using traditional, high-effort gate-level analysis. Moreover, the new methodology produces waveforms identical (or nearly identical) to those generated by gate-level simulation. Consequently, the design can be analyzed and optimized iteratively throughout the post-synthesis design flow, enabling much earlier detection and easier resolution of power issues. The paper discusses:

• Power analysis challenge 
• New automated gate-level waveform methodology
• Springsoft’s Siloti™ Visibility Automation System
• Analysis results

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