The next transistor: planar, fins, and SoI at 22nm

Ron Wilson, EETimes
7/19/2011 3:59 PM EDT

The race is on to redefine the transistor. Process developers working on 22/20nm logic processes appear to be scrambling to introduce new kinds of transistors for this node. Intel has made a huge fanfare over their tri-gate device. Many researchers are pushing finFETs. A powerful group of mainly European organizations, including ARM and US-based Globalfoundries, is serious about fully-depleted SoI (fdSoI.) And recently, start-up Suvolta and Fujitsu described yet another alternative.

All this might appear fascinating for device designers, and irrelevant to chip designers. But decisions on transistor design will have profound downstream impacts—from the craft of cell design to the work of physical-design teams, and even to the logic designer’s struggles with power and timing closure.

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