The next transistor: planar, fins, and SoI at 22nm
Ron Wilson, EETimes
7/19/2011 3:59 PM EDT
The race is on to redefine the transistor. Process developers working on 22/20nm logic processes appear to be scrambling to introduce new kinds of transistors for this node. Intel has made a huge fanfare over their tri-gate device. Many researchers are pushing finFETs. A powerful group of mainly European organizations, including ARM and US-based Globalfoundries, is serious about fully-depleted SoI (fdSoI.) And recently, start-up Suvolta and Fujitsu described yet another alternative.
All this might appear fascinating for device designers, and irrelevant to chip designers. But decisions on transistor design will have profound downstream impacts—from the craft of cell design to the work of physical-design teams, and even to the logic designer’s struggles with power and timing closure.
To read the full article, click here
Related Semiconductor IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- 1G BASE-T Ethernet Verification IP
- Network-on-Chip (NoC)
- Microsecond Channel (MSC/MSC-Plus) Controller
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
Related Articles
- Do Standardized Embedded IP Transistor Views Exist for SoC IP Integration?
- Strained SOI on the move to mainstream
- Design myths surround strained SOI
- SOI eases radiation-hardened ASIC designs
Latest Articles
- Extending and Accelerating Inner Product Masking with Fault Detection via Instruction Set Extension
- ioPUF+: A PUF Based on I/O Pull-Up/Down Resistors for Secret Key Generation in IoT Nodes
- In-Situ Encryption of Single-Transistor Nonvolatile Memories without Density Loss
- David vs. Goliath: Can Small Models Win Big with Agentic AI in Hardware Design?
- RoMe: Row Granularity Access Memory System for Large Language Models