Timing closure in multi-level partitioned SoCs
Syed Shakir Iqbal , Mitul Soni & Gourav Kapoor (Freescale)
EDN (October 07, 2015)
With rising SoC design complexity, hierarchical backend design closure has become almost ubiquitous across the industry. Block and sub-block partitioning allow designers to exploit engineering and tool bandwidth more efficiently through optimized resource use. In addition, this approach is compatible with a bottom-to-top design approach.
This is in keeping with design practice wherein mature IP partitions are taken into the backend cycle while work is going on to finish the rest of the chip. Benefits like design-cycle reduction have prompted designers to push for multi-level partitioning schemes. However, as the level of hierarchical partitions increases, so do the challenges involved in their closure and signoff.
In this paper, we discuss the major timing and implementation challenges involved in multi-level hierarchical partitioning and modeling schemes.
To read the full article, click here
Related Semiconductor IP
- HBM4 PHY IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- HBM4 Controller IP
- IPSEC AES-256-GCM (Standalone IPsec)
- Parameterizable compact BCH codec
Related Articles
- FPGA prototyping of complex SoCs: Partitioning and Timing Closure Challenges with Solutions
- Complex SoCs: Early Use of Physical Design Info Shortens Timing Closure
- Timing Closure on FPGAs
- Latches and timing closure: a mixed bag
Latest Articles
- A 14ns-Latency 9Gb/s 0.44mm² 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX
- Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor
- Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing
- Leveraging FPGAs for Homomorphic Matrix-Vector Multiplication in Oblivious Message Retrieval
- Extending and Accelerating Inner Product Masking with Fault Detection via Instruction Set Extension