Timing closure in multi-level partitioned SoCs
Syed Shakir Iqbal , Mitul Soni & Gourav Kapoor (Freescale)
EDN (October 07, 2015)
With rising SoC design complexity, hierarchical backend design closure has become almost ubiquitous across the industry. Block and sub-block partitioning allow designers to exploit engineering and tool bandwidth more efficiently through optimized resource use. In addition, this approach is compatible with a bottom-to-top design approach.
This is in keeping with design practice wherein mature IP partitions are taken into the backend cycle while work is going on to finish the rest of the chip. Benefits like design-cycle reduction have prompted designers to push for multi-level partitioning schemes. However, as the level of hierarchical partitions increases, so do the challenges involved in their closure and signoff.
In this paper, we discuss the major timing and implementation challenges involved in multi-level hierarchical partitioning and modeling schemes.
To read the full article, click here
Related Semiconductor IP
- DeWarp IP
- 6-bit, 12 GSPS Flash ADC - GlobalFoundries 22nm
- LunaNet AFS LDPC Encoder and Decoder IP Core
- ReRAM NVM in DB HiTek 130nm BCD
- UFS 5.0 Host Controller IP
Related Articles
- FPGA prototyping of complex SoCs: Partitioning and Timing Closure Challenges with Solutions
- Complex SoCs: Early Use of Physical Design Info Shortens Timing Closure
- Timing Closure on FPGAs
- Latches and timing closure: a mixed bag
Latest Articles
- VolTune: A Fine-Grained Runtime Voltage Control Architecture for FPGA Systems
- A Lightweight High-Throughput Collective-Capable NoC for Large-Scale ML Accelerators
- Quantifying Uncertainty in FMEDA Safety Metrics: An Error Propagation Approach for Enhanced ASIC Verification
- SoK: From Silicon to Netlist and Beyond Two Decades of Hardware Reverse Engineering Research
- An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks