The RapidIO High-Speed Interconnect: A Technical Overview

Today's high-speed embedded applications are like networks unto themselves. They possess tremendous processing resources capable of acquiring and analyzing large amounts of data that require a complex internal fabric to facilitate the transfer of data throughout the system. Data often passes through many interconnect layers and protocols as it crosses the fabric, with each layer of interconnect introducing undesirable latency, complexity, and cost (see Figure 1).

In order to achieve the performance required for these applications (many of which must produce results in real-time with the minimum latency) developers are seeking ways to consolidate interconnect layers across the system. Not only are they trying to more seamlessly connect chips, boards, and chassis, ideally they'd like to collapse the data and control planes into a single fabric.

A system-level interconnect must perform efficiently and offer the mix of functionality appropriate for the data it is to transport. Developers aiming to achieve the highest performance and reliability understand that selecting the optimal interconnect for a system fabric involves a great many considerations beyond theoretical maximum throughput, including how efficiency is an inherent part of the physical, transport, and logical layers and features such as multiple physical layer (PHY) options, deadlock avoidance through priority mechanisms and buffer management, advanced quality of service with short- and long-term flow control mechanisms, and data plane capabilities that enable the interconnect to transport any protocol.
By Greg Shippen, Freescale Semiconductor
(10/08/07, 03:12:00 PM EDT) -- CommsDesign

Today's high-speed embedded applications are like networks unto themselves. They possess tremendous processing resources capable of acquiring and analyzing large amounts of data that require a complex internal fabric to facilitate the transfer of data throughout the system. Data often passes through many interconnect layers and protocols as it crosses the fabric, with each layer of interconnect introducing undesirable latency, complexity, and cost (see Figure 1).

In order to achieve the performance required for these applications (many of which must produce results in real-time with the minimum latency) developers are seeking ways to consolidate interconnect layers across the system. Not only are they trying to more seamlessly connect chips, boards, and chassis, ideally they'd like to collapse the data and control planes into a single fabric.

A system-level interconnect must perform efficiently and offer the mix of functionality appropriate for the data it is to transport. Developers aiming to achieve the highest performance and reliability understand that selecting the optimal interconnect for a system fabric involves a great many considerations beyond theoretical maximum throughput, including how efficiency is an inherent part of the physical, transport, and logical layers and features such as multiple physical layer (PHY) options, deadlock avoidance through priority mechanisms and buffer management, advanced quality of service with short- and long-term flow control mechanisms, and data plane capabilities that enable the interconnect to transport any protocol.

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