The Network Switch: Unsung Hero of the Hyper-Scale Data Center
By Tom Wong, Cadence
EETimes (October 5, 2021)
While we typically associate low power with battery-operated devices such as smartphones, smart watches and laptops, there are several other less obvious applications where low power has a significant impact on our daily lives. One such example is all the “plumbing” and communications infrastrutction, often referred to as high-performance computing, managed by network switches inside a modern hyper-scale data center.
With the explosive growth of online activities driven by work from home, many industry sectors sectors are reporting huge growth in internet usage and e-commerce. We work, learn, play from home while embracing e-commerce and online delivery, telemedicine, virtual fitness and a host of other virtual events and experiences. And all of it seems to have moved to the cloud.
In the early 2010s, close to 40 percent of large companies surveyed said they expected to exceed their IT capacity within two years. Almost a decade later, virtually all businesses, regardless of size or sector, rely heavily on technology to scale and streamline their operations. More than ever, access to massive volumes of data is vital to their success. To increase their ability to process all this data quickly, these businesses must secure more computing and storage capacity from cloud providers who are building out massive data centers across while accelerating deployment of next-generation technology.
To read the full article, click here
Related Semiconductor IP
Related White Papers
- Data Movement Is the Energy Bottleneck of Today’s SoCs
- Reimagining AI Infrastructure: The Power of Converged Back-end Networks
- The Elements of Traceability
- Out of the Verification Crisis: Improving RTL Quality
Latest White Papers
- OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
- Balancing Power and Performance With Task Dependencies in Multi-Core Systems
- LLM Inference with Codebook-based Q4X Quantization using the Llama.cpp Framework on RISC-V Vector CPUs
- PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions
- Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS