The need for verification management
Ilana Golan, Cadence Design Systems
(06/05/2006 9:00 AM EDT), EE Times
Project management and automation are quickly becoming the most critical elements of the design and verification process. The key ingredients are good specification development and metric-based checkpoints. The ability to "begin with the end in mind" allows for optimal resource usage, much higher design quality and realistic schedule estimates for customers.
Today's design and verification flows often miss cross-functional problems. The flows tend to focus primarily on individual tasks, engine performance or languages, rather than on defining the entire verification challenge or team interdependencies. In fact, most verification plans are merely a set of incomplete discussion notes that atrophy as the project moves forward.
Good management of the design and verification process starts with specific goals that focus on what needs to be verified. Using those guidelines, an experienced verification team can develop and implement a plan that includes everything. Stakeholders can capture and review the verification plan to drive the design safely and smoothly to closure.
Successful verification management requires good analysis of the specification, an awareness of the scope of the job at hand, and a firm decision on what coverage models and metrics to track. Here are some of the basic do's and don'ts to keep in mind.
(06/05/2006 9:00 AM EDT), EE Times
Project management and automation are quickly becoming the most critical elements of the design and verification process. The key ingredients are good specification development and metric-based checkpoints. The ability to "begin with the end in mind" allows for optimal resource usage, much higher design quality and realistic schedule estimates for customers.
Today's design and verification flows often miss cross-functional problems. The flows tend to focus primarily on individual tasks, engine performance or languages, rather than on defining the entire verification challenge or team interdependencies. In fact, most verification plans are merely a set of incomplete discussion notes that atrophy as the project moves forward.
Good management of the design and verification process starts with specific goals that focus on what needs to be verified. Using those guidelines, an experienced verification team can develop and implement a plan that includes everything. Stakeholders can capture and review the verification plan to drive the design safely and smoothly to closure.
Successful verification management requires good analysis of the specification, an awareness of the scope of the job at hand, and a firm decision on what coverage models and metrics to track. Here are some of the basic do's and don'ts to keep in mind.
To read the full article, click here
Related Semiconductor IP
- LPDDR6/5X/5 PHY V2 - Intel 18A-P
- ML-KEM Key Encapsulation & ML-DSA Digital Signature Engine
- MIPI SoundWire I3S Peripheral IP
- ML-DSA Digital Signature Engine
- P1619 / 802.1ae (MACSec) GCM/XTS/CBC-AES Core
Related White Papers
- Efficient methodology for design and verification of Memory ECC error management logic in safety critical SoCs
- Out of the Verification Crisis: Improving RTL Quality
- Differentiation Through the Chip Design and Verification Flow
- IC design: A short primer on the formal methods-based verification
Latest White Papers
- AnaFlow: Agentic LLM-based Workflow for Reasoning-Driven Explainable and Sample-Efficient Analog Circuit Sizing
- FeNN-DMA: A RISC-V SoC for SNN acceleration
- Multimodal Chip Physical Design Engineer Assistant
- An AUTOSAR-Aligned Architectural Study of Vulnerabilities in Automotive SoC Software
- Attack on a PUF-based Secure Binary Neural Network