Using SystemVue to overcome 4G challenges
Daren McClearnon and Wu Huan, Agilent Technologies
12/5/2011 9:59 AM EST
LTE-Advanced (LTE-A) is an emerging mobile communications standard being developed by 3GPP. Specified as part of Release 10 of the 3GPP specifications, it is now approved for 4G IMT-Advanced. LTE-A leverages many existing LTE Release 8/9 parameters, while also incorporating a number of enhancements, including carrier aggregation, an enhanced multiple access scheme and MIMO transmission, multi-hop transmission, coordinated multipoint (CoMP) transmission/reception, and support for heterogeneous networks. These enhancements enable significant benefits, but they also create baseband and RF design challenges that further complicate the 4G physical layer (PHY) architecture development. Next-generation Electronic Design Automation (EDA) tools, with their array of new capabilities, offer a viable resolution to this dilemma. The trick is in understanding what these new capabilities are and how they can be used to overcome 4G challenges.
A number of EDA tools available on the market today can be used for LTE-based design; however, creating superior systems designs for the emerging LTE-A standard requires an entirely new set of functionality.
To read the full article, click here
Related Semiconductor IP
- HBM4 PHY IP
- eFuse Controller IP
- Secure Storage Solution for OTP IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
Related Articles
- FAUST: On-Chip Distributed SoC Architecture for a 4G Baseband Modem Chipset
- Overcome power, size and cost when developing optimized '4G' chipsets for handhelds
- Using signal compression to ease migration to a 4G wireless infrastructure
- Power-efficient SDR platform handles multimode 4G
Latest Articles
- Making Strong Error-Correcting Codes Work Effectively for HBM in AI Inference
- Sensitivity-Aware Mixed-Precision Quantization for ReRAM-based Computing-in-Memory
- ElfCore: A 28nm Neural Processor Enabling Dynamic Structured Sparse Training and Online Self-Supervised Learning with Activity-Dependent Weight Update
- A 14ns-Latency 9Gb/s 0.44mm² 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX
- Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor