Only 10 days to shipping ... we may have a memory problem!
Clive ‘Max’ Maxfield and Joe Skazinski
EETimes (12/21/2010 12:24 PM EST)
This paper describes how software development engineers using OMAP, Sitara, QorIQ, PowerQUICC, and PowerPC processors can fully validate their hardware platform and integrate their final application prior to customer shipment.
How many times have you been in a situation working with a new system where the board bring-up occurred without any major problems manifesting themselves? Initially, everything seems to work just fine. The rudimentary diagnostic tests provided by the hardware guys indicate that all is as it should be. The application software appears to be working as planned. The customer ship date is fast approaching. Everyone on the team is starting to feel confident, but with only a few days to go, everything grinds to a halt.
Possibly an application is attempting some new task for the first time – perhaps a DMA transfer with the CPU cache disabled. But why is the system crashing? Surely someone must have validated this mode of operation, didn’t they?
To read the full article, click here
Related Semiconductor IP
- JESD204E Controller IP
- eUSB2V2.0 Controller + PHY IP
- I/O Library with LVDS in SkyWater 90nm
- 50G PON LDPC Encoder/Decoder
- UALink Controller
Related Articles
- New Realities Demand a New Approach to System Verification and Validation
- Doing ESL system validation using transactors
- Reduce SoC verification time through reuse in pre-silicon validation
- Bridging the Gap between Pre-Silicon Verification and Post-Silicon Validation in Networking SoC designs
Latest Articles
- Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT Security
- In-Pipeline Integration of Digital In-Memory-Computing into RISC-V Vector Architecture to Accelerate Deep Learning
- QMC: Efficient SLM Edge Inference via Outlier-Aware Quantization and Emergent Memories Co-Design
- ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design
- COVERT: Trojan Detection in COTS Hardware via Statistical Activation of Microarchitectural Events