Only 10 days to shipping ... we may have a memory problem!
Clive ‘Max’ Maxfield and Joe Skazinski
EETimes (12/21/2010 12:24 PM EST)
This paper describes how software development engineers using OMAP, Sitara, QorIQ, PowerQUICC, and PowerPC processors can fully validate their hardware platform and integrate their final application prior to customer shipment.
How many times have you been in a situation working with a new system where the board bring-up occurred without any major problems manifesting themselves? Initially, everything seems to work just fine. The rudimentary diagnostic tests provided by the hardware guys indicate that all is as it should be. The application software appears to be working as planned. The customer ship date is fast approaching. Everyone on the team is starting to feel confident, but with only a few days to go, everything grinds to a halt.
Possibly an application is attempting some new task for the first time – perhaps a DMA transfer with the CPU cache disabled. But why is the system crashing? Surely someone must have validated this mode of operation, didn’t they?
To read the full article, click here
Related Semiconductor IP
- HBM4 PHY IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
- HBM4 Controller IP
- IPSEC AES-256-GCM (Standalone IPsec)
Related Articles
- New Realities Demand a New Approach to System Verification and Validation
- Doing ESL system validation using transactors
- Reduce SoC verification time through reuse in pre-silicon validation
- Bridging the Gap between Pre-Silicon Verification and Post-Silicon Validation in Networking SoC designs
Latest Articles
- A 14ns-Latency 9Gb/s 0.44mm² 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX
- Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor
- Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing
- Leveraging FPGAs for Homomorphic Matrix-Vector Multiplication in Oblivious Message Retrieval
- Extending and Accelerating Inner Product Masking with Fault Detection via Instruction Set Extension