Putting the system in electronic system design
Ken Karnofsky, The MathWorks
(02/04/2008 9:00 AM EST), EE Times
You've heard it before. Increasingly complex systems and technologies like multicore processors and FPGAs have rendered old design methodologies obsolete. New approaches are needed: system-level abstractions that handle complexity, and tools that automate the costly, time-consuming steps between concept and implementation.
Within the realm of processor-centric system-on-chip design and verification, electronic system-level (ESL) methods aim to address some of the problems. Various approaches and commercial tools have been introduced (and others repackaged) since EDA analyst Gary Smith coined the term ESL several years ago. The tools enable hardware designers to model complex SoC architectures, permitting software developers to start writing code before hardware is available, and in some cases aiding hardware component implementation.
But the narrow scope of most ESL approaches and tools has limited their adoption. A more encompassing methodology, one that steps beyond the SoC, is needed to slash time, cost and errors in complex system development. The new methodology should:
(02/04/2008 9:00 AM EST), EE Times
You've heard it before. Increasingly complex systems and technologies like multicore processors and FPGAs have rendered old design methodologies obsolete. New approaches are needed: system-level abstractions that handle complexity, and tools that automate the costly, time-consuming steps between concept and implementation.
Within the realm of processor-centric system-on-chip design and verification, electronic system-level (ESL) methods aim to address some of the problems. Various approaches and commercial tools have been introduced (and others repackaged) since EDA analyst Gary Smith coined the term ESL several years ago. The tools enable hardware designers to model complex SoC architectures, permitting software developers to start writing code before hardware is available, and in some cases aiding hardware component implementation.
But the narrow scope of most ESL approaches and tools has limited their adoption. A more encompassing methodology, one that steps beyond the SoC, is needed to slash time, cost and errors in complex system development. The new methodology should:
To read the full article, click here
Related Semiconductor IP
- JESD204E Controller IP
- eUSB2V2.0 Controller + PHY IP
- I/O Library with LVDS in SkyWater 90nm
- 50G PON LDPC Encoder/Decoder
- UALink Controller
Related Articles
- Emerging Trends and Challenges in Embedded System Design
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Understanding LTTPR: Enabling High-Speed DisplayPort Interconnects in Complex System Designs
- Software Architecture for IP verification in Operating System environment
Latest Articles
- Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT Security
- In-Pipeline Integration of Digital In-Memory-Computing into RISC-V Vector Architecture to Accelerate Deep Learning
- QMC: Efficient SLM Edge Inference via Outlier-Aware Quantization and Emergent Memories Co-Design
- ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design
- COVERT: Trojan Detection in COTS Hardware via Statistical Activation of Microarchitectural Events