Stretching the Dynamic Range of ADCs - A case study
Robert Fifield, RFEL
EETimes (10/9/2012 10:26 AM EDT)
Whether your application is focused on wireless communications or instrumentation, the performance bottleneck is often the dynamic range of the analog-to-digital converter (ADC). Dynamic range is often a key parameter within signal processing systems and a shortfall can limit the quality and range of signals that can be received. The technical progress made on improving this gateway between the analog and digital world has not kept pace with Moore’s law[1] because the challenges are more fundamental than simply reducing transistor sizes. Methods to increase ADC dynamic range are always of interest although each solution often suits particular applications.
As an example of pushing ADC dynamic range beyond what is currently available, the engineers at RFEL were confronted with an application where a customer required an analog-to-digital conversion with a 74dB dynamic range at 800MSPS. Most available ADCs at this rate were typically 52dB, i.e. 8.3 effective number of bits[2] (ENOB). This represented a significant 22dB shortfall, which had to be resolved for the project to be feasible.
Various techniques for extending dynamic range were considered taking into account their advantages and disadvantages:
To read the full article, click here
Related Semiconductor IP
- ADC
- 14-bit 12.5MSPS SAR ADC - Tower 65nm
- Ultra high-performance low-power ADC
- 10-bit SAR ADC - XFAB XT018
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
Related Articles
- Inside HDR10: A technical exploration of High Dynamic Range
- Variable-integration-time image sensor for wide dynamic range
- New Applications Areas Driving Higher Dynamic Range Converters
- The Elements of Traceability
Latest Articles
- SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks
- An FPGA Implementation of Displacement Vector Search for Intra Pattern Copy in JPEG XS
- A Persistent-State Dataflow Accelerator for Memory-Bound Linear Attention Decode on FPGA
- VMXDOTP: A RISC-V Vector ISA Extension for Efficient Microscaling (MX) Format Acceleration
- PDF: PUF-based DNN Fingerprinting for Knowledge Distillation Traceability