Software-to-silicon verification @ 45 nm and beyond
EE Times (07/13/2009 12:01 AM EDT)
Chip and system developers once considered verification as a secondary activity following the main challenge of design, with the "Designer" playing the central role in a design's success. This notion is firmly turned on its head today, as verification is the biggest component of chip hardware development budgets, schedules, staffing and risk.
With verification complexity growing faster than Moore's Law, compounded by increasing mixed-signal content and advanced low-power design techniques, the importance of verification in the chip hardware development process is certain to increase. In fact, venture capitalists have started focusing on verification costs as a factor in determining which chip startups to fund. Similarly, embedded software used to be a minor or nonexistent deliverable for typical semiconductor devices. At 45 nm and beyond, software accounts for a full 60 percent of total chip-development cost, with major implications on how chips and systems are verified. It is no surprise, then, that the International Technology Roadmap for Semiconductors (ITRS) predicts that, "Without major breakthroughs, verification will be a non-scalable, show-stopping barrier to further progress in the semiconductor industry."
To read the full article, click here
Related Semiconductor IP
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- USB 20Gbps Device Controller
- SM4 Cipher Engine
- Ultra-High-Speed Time-Interleaved 7-bit 64GSPS ADC on 3nm
- Fault Tolerant DDR2/DDR3/DDR4 Memory controller
Related White Papers
- Verification challenges of ADC subsystem integration within an SoC
- Can Hardware-Assisted Verification Save SoC Realization Time?
- Formal, simulation, and AMBA verification IP combine to verify configurable powerline networking SoC
- Mixed Signal Design & Verification Methodology for Complex SoCs
Latest White Papers
- Fault Injection in On-Chip Interconnects: A Comparative Study of Wishbone, AXI-Lite, and AXI
- eFPGA – Hidden Engine of Tomorrow’s High-Frequency Trading Systems
- aTENNuate: Optimized Real-time Speech Enhancement with Deep SSMs on RawAudio
- Combating the Memory Walls: Optimization Pathways for Long-Context Agentic LLM Inference
- Hardware Acceleration of Kolmogorov-Arnold Network (KAN) in Large-Scale Systems