Secure in-system programming for FPGAs
By Michael Mertz, Actel Corporation
Programmable Logic DesignLine
(10/26/2005 2:53 PM EDT)
Controlling access to - and protecting the intellectual property inside - an FPGA is a requirement known as "Secure ISP"
FPGAs are being chosen more and more frequently to comprise the heart of the modern electronic system. There are several possible reasons for this – low cost, ready availability and increasing sophistication of FPGAs – but chief among these must certainly be the ease with which FPGA hardware can be reconfigured to adapt to potential changes in the system specification.
Hardware reprogrammability is the "killer app" that is realized in FPGA devices. The benefits are numerous. In addition to the obvious benefit of changing the function of the silicon with virtually no additional cost – a huge advantage over conventional ASICs – the ability to respond to changes in specifications, add features, or configure customer preferences "on-the-fly" virtually guarantees longer product lifecycles and improved profitability.
An extremely important consideration is the extent to which the FPGA program can be configured safely in situ – i.e., with in-system programming (ISP) – such that system designers accrue the greatest benefit. It is clearly desirable to be able to change the system program after the system has been completely fabricated, indeed, even when the system is deployed in the field. It is also desirable, in most cases, to control when the device is reprogrammed and to do it securely. In short, a complete package of capabilities to control access to and protect the intellectual property inside the FPGA is a requirement known as "Secure ISP."
Programmable Logic DesignLine
(10/26/2005 2:53 PM EDT)
Controlling access to - and protecting the intellectual property inside - an FPGA is a requirement known as "Secure ISP"
FPGAs are being chosen more and more frequently to comprise the heart of the modern electronic system. There are several possible reasons for this – low cost, ready availability and increasing sophistication of FPGAs – but chief among these must certainly be the ease with which FPGA hardware can be reconfigured to adapt to potential changes in the system specification.
Hardware reprogrammability is the "killer app" that is realized in FPGA devices. The benefits are numerous. In addition to the obvious benefit of changing the function of the silicon with virtually no additional cost – a huge advantage over conventional ASICs – the ability to respond to changes in specifications, add features, or configure customer preferences "on-the-fly" virtually guarantees longer product lifecycles and improved profitability.
An extremely important consideration is the extent to which the FPGA program can be configured safely in situ – i.e., with in-system programming (ISP) – such that system designers accrue the greatest benefit. It is clearly desirable to be able to change the system program after the system has been completely fabricated, indeed, even when the system is deployed in the field. It is also desirable, in most cases, to control when the device is reprogrammed and to do it securely. In short, a complete package of capabilities to control access to and protect the intellectual property inside the FPGA is a requirement known as "Secure ISP."
To read the full article, click here
Related Semiconductor IP
- ReRAM NVM in DB HiTek 130nm BCD
- UFS 5.0 Host Controller IP
- PDM Receiver/PDM-to-PCM Converter
- Voltage and Temperature Sensor with integrated ADC - GlobalFoundries® 22FDX®
- 8MHz / 40MHz Pierce Oscillator - X-FAB XT018-0.18µm
Related Articles
- Growing demand for high-speed data in consumer devices gives rise to new generation of low-end FPGAs
- Leveraging FPGAs for Homomorphic Matrix-Vector Multiplication in Oblivious Message Retrieval
- IMS: Intelligent Hardware Monitoring System for Secure SoCs
- How to use FPGAs to develop an intelligent solar tracking system
Latest Articles
- An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks
- Enabling RISC-V Vector Code Generation in MLIR through Custom xDSL Lowerings
- A Scalable Open-Source QEC System with Sub-Microsecond Decoding-Feedback Latency
- SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks
- An FPGA Implementation of Displacement Vector Search for Intra Pattern Copy in JPEG XS