Scaling a video on demand server
Early performance estimation is key to successful implementation
Illia Cremer, CoFluent Design
EETimes (4/27/2011 9:51 AM EDT)
Abstract
In a growing and more competitive video on demand (VoD) market, system designers face new challenges in VoD server infrastructures definition and sizing. Early performance estimation thanks to abstract modeling is a key enabler for providing best quality of service and compelling user experience.
This article illustrates how to model and simulate an example model of a RTP/RTSP video on demand server using the method, notations and tools provided by CoFluent Design.
The objective is to determine the client’s frame rate deviation and the average power consumption for different server configurations. The frame rate deviation is the difference between the expected theoretical frame rate and the actual frame rate of the video stream. It directly impacts the user’s watching experience and should be kept as much as possible close to zero.
The impact of different hardware elements of the server such as HDD type and server buffering is studied. The example also illustrates how to model multiple instances of the same function, and how to define an abstract network of computers.
To read the full article, click here
Related Semiconductor IP
- HBM4 PHY IP
- eFuse Controller IP
- Secure Storage Solution for OTP IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
Related Articles
- Using vector processing for HD video scaling, de-interlacing, and image customization
- Polyphase Video Scaling in FPGAs
- Revisiting the analogue video decoder: Brushing up on your comb filters
- Thoughts on Streaming Video Securely
Latest Articles
- Making Strong Error-Correcting Codes Work Effectively for HBM in AI Inference
- Sensitivity-Aware Mixed-Precision Quantization for ReRAM-based Computing-in-Memory
- ElfCore: A 28nm Neural Processor Enabling Dynamic Structured Sparse Training and Online Self-Supervised Learning with Activity-Dependent Weight Update
- A 14ns-Latency 9Gb/s 0.44mm² 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX
- Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor