Power mode technologies verify today's SoCs
Tom Anderson, Cadence Design Systems
(02/27/2008 9:32 AM EST) -- EE Times
The power architectures on today's power-cycled system-on-chip designs can be distressingly complex. Multiple power domains with many power modes require a thorough verification process.
Five technologies " PDML specification, power-aware simulation, structural power checks, power-related assertions and formal analysis of the power control logic " provide outstanding checking and coverage while shaving half the power verification time. These technologies are the key components of an effective power verification methodology to ensure that low-power design produces high-confidence chips.
In today's power-cycled systems-on-chip (SoCs), the power budget is lowered by reducing or shutting off power to regions of the device known as power domains. First-generation power-cycled SoC designs have only a few power domains, but newer designs now under development will feature as many as 20, producing numerous power modes.
(02/27/2008 9:32 AM EST) -- EE Times
The power architectures on today's power-cycled system-on-chip designs can be distressingly complex. Multiple power domains with many power modes require a thorough verification process.
Five technologies " PDML specification, power-aware simulation, structural power checks, power-related assertions and formal analysis of the power control logic " provide outstanding checking and coverage while shaving half the power verification time. These technologies are the key components of an effective power verification methodology to ensure that low-power design produces high-confidence chips.
In today's power-cycled systems-on-chip (SoCs), the power budget is lowered by reducing or shutting off power to regions of the device known as power domains. First-generation power-cycled SoC designs have only a few power domains, but newer designs now under development will feature as many as 20, producing numerous power modes.
To read the full article, click here
Related Semiconductor IP
- JESD204E Controller IP
- eUSB2V2.0 Controller + PHY IP
- I/O Library with LVDS in SkyWater 90nm
- 50G PON LDPC Encoder/Decoder
- UALink Controller
Related Articles
- Unified Methodology for Effective Correlation of SoC Power Estimation and Signoff
- Improving Battery-Powered Device Operation Time Thanks To Power Efficient Sleep Mode
- Low Power Design in SoC Using Arm IP
- eFPGAs Bring a 10X Advantage in Power and Cost
Latest Articles
- Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT Security
- In-Pipeline Integration of Digital In-Memory-Computing into RISC-V Vector Architecture to Accelerate Deep Learning
- QMC: Efficient SLM Edge Inference via Outlier-Aware Quantization and Emergent Memories Co-Design
- ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design
- COVERT: Trojan Detection in COTS Hardware via Statistical Activation of Microarchitectural Events