PCI Express verification underscores need to plan
(11/07/2005 10:00 AM EST)
EE Times
PCI Express-based designs are textbook examples of a complex verification problem. Using a compliance checklist can kick-start verification planning. But you also need a well-planned verification methodology that addresses these questions: What compliance items are verified? Have you covered all compliance scenarios? Can you provide a progress report to your manager?
These challenges are not new for verification engineers. But complex verification projects force the extended team to do more planning, to avoid getting lost in the 1,300+ item compliance checklist.
An extensive checklist can serve as a compliance verification plan to identify how to co-relate compliance items to the data automatically provided by the verification environment. This involves mapping English definitions to a mechanism. Often, we underestimate the workload and get confused between checking a single scenario and proving that a specific feature works in all scenarios.
To read the full article, click here
Related Semiconductor IP
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- NPU IP Core for Mobile
Related White Papers
- PCI Express 3.0 needs reliable timing design
- PCI Express 3.0 needs reliable timing design
- Automotive Design Needs Efficient Verification to Survive
- How HyperTransport and PCI Express complement each other
Latest White Papers
- QiMeng: Fully Automated Hardware and Software Design for Processor Chip
- RISC-V source class riscv_asm_program_gen, the brain behind assembly instruction generator
- Concealable physical unclonable functions using vertical NAND flash memory
- Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
- Transition Fixes in 3nm Multi-Voltage SoC Design