The best of both worlds: Optimizing OCP slave memory behavior
By Neill Mullinger, Synopsys, Inc. EDA DesignLine
(11/09/2009 0:56 AM EST)
Verification IP for OCP is generally used to achieve one of two main verification objectives; at the module level to test OCP components and their interfaces; or at the bus fabric level when some or all of the components may be replaced by the verification IP to test the behavior of a system. In either case, the VIP behavior used in verification will ultimately be replaced with a real component or interface, and so it is important that the verification IP can represent the behavior of the real component or components; even better to represent a spread of components that might be used in conjunction with the design being tested. The real slave components in an OCP design will have memory of one form or another and so accurately modeling the behavior of the memory in the verification IP can be critical to understanding system performance and identifying potential hazards.
To read the full article, click here
Related Semiconductor IP
- Post-Quantum Digital Signature IP Core
- Compact Embedded RISC-V Processor
- Power-OK Monitor
- RISC-V-Based, Open Source AI Accelerator for the Edge
- Securyzr™ neo Core Platform
Related White Papers
- Optimizing high-performance CPUs, GPUs and DSPs? Use logic and memory IP - Part I
- Optimizing High Performance CPUs, GPUs and DSPs? Use logic and memory IP - Part II
- Optimizing data memory utilization
- Optimizing flash memory selection for automotive & other uses
Latest White Papers
- DRsam: Detection of Fault-Based Microarchitectural Side-Channel Attacks in RISC-V Using Statistical Preprocessing and Association Rule Mining
- ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors
- Practical Considerations of LDPC Decoder Design in Communications Systems
- A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems
- A logically correct SoC design isn’t an optimized design