On hardware dependencies and scrum
Mike Hogg, Zuhlke
embedded.com (January 22, 2014)
Embedded systems require hardware. We've experienced successful hardware development following agile principles, in particular by ASIC and FPGA teams. Nevertheless, many hardware engineers find it impossible to follow an agile approach; their "design -- manufacture -- assemble -- test" lifecycle is often too long and expensive for such an iterative incremental scheme. How can agile software developers work with such hardware engineers?
Let's focus on running a scrum process when there are inter-dependencies with a non-agile team. Advice on managing this scenario is rare.
Agile teams work on user stories that describe the functionality to be delivered. These are collected in a product backlog. Should user stories only cover software features? No, in the embedded space software alone is insufficient to make a product. Rather, we can use top level stories (known as epics) that reflect the combined software and hardware development needed, and are understood by both disciplines. The software team will likely break these epics down in to a series of smaller constituent user stories for the software features, while the hardware team may manage their work differently.
To read the full article, click here
Related Semiconductor IP
- Flexible Pixel Processor Video IP
- Bluetooth Low Energy 6.0 Digital IP
- MIPI SWI3S Manager Core IP
- Ultra-low power high dynamic range image sensor
- Neural Video Processor IP
Related White Papers
- Interstellar: Fully Partitioned and Efficient Security Monitoring Hardware Near a Processor Core for Protecting Systems against Attacks on Privileged Software
- A Survey on the Design, Detection, and Prevention of Pre-Silicon Hardware Trojans
- SoC interconnect performance verification methodology based on hardware emulator
- HW/SW Interface Generation Flow Based on Abstract Models of System Applications and Hardware Architectures
Latest White Papers
- Enabling Space-Grade AI/ML with RISC-V: A Fully European Stack for Autonomous Missions
- CANDoSA: A Hardware Performance Counter-Based Intrusion Detection System for DoS Attacks on Automotive CAN bus
- How Next-Gen Chips Are Unlocking RISC-V’s Customization Advantage
- Efficient Hardware-Assisted Heap Memory Safety for Embedded RISC-V Systems
- Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions