Managing IP quality in the SoC era requires a purpose-built DM approach
Simon Butler, CEO, Methodics LLC
EETimes (9/19/2011 12:01 AM EDT)
With the steady advancement of manufacturing process geometries enabling new levels of integration on a single chip, the use of IP – whether internally developed or sourced from a third-party – has become more complex. Such complexity is inherent in any type of process where more elements are introduced (i.e. IP blocks), and is compounded by factors such as geographically diverse design teams, a lack of standard metrics for IP use and quality, and shifting design parameters. A modern SoC development project has a plethora of "moving parts." While there are many tools available to help verify, debug and otherwise manipulate IP, there has been a distinct lack of a solid design data management system to address the specific needs of SoC designers in this type of dynamic environments.
As a result, IP use in general often suffers from a bad rap in terms of quality. The term IP quality has different meanings to different people, but in general terms it refers to 1) the functional correctness of the IP – does it work they way it is supposed to (i.e. bug free)"; and 2) does it do what I need it to do with respect to my design parameters – power, timing, area, etc.? Developing and integrating quality IP by either or both of those definitions requires a system that can effectively track changes and input across the entire design team at the desktop level, provide real-time access to a wide range of meta data and quality information on IP, as well as keep project managers and other senior management informed on how the use of IP is impacting schedules, budgets and design resources. Without accurate and current quality metrics for dependent IP components designers are often forced to overdesign using pessimistic slack definitions, unrealistic size information, inaccurate power estimates etc. A system cognizant of the IP versions in a users current context, with up to date metrics for dependent blocks provides a truly collaborative and accurate development environment, which translates to reduced development cycles and cost.
To read the full article, click here
Related Semiconductor IP
- ReRAM NVM in DB HiTek 130nm BCD
- UFS 5.0 Host Controller IP
- PDM Receiver/PDM-to-PCM Converter
- Voltage and Temperature Sensor with integrated ADC - GlobalFoundries® 22FDX®
- 8MHz / 40MHz Pierce Oscillator - X-FAB XT018-0.18µm
Related Articles
- Agile Analog's Approach to Analog IP Design and Quality --- Why "Silicon Proven" is NOT What You Think
- Keeping the best audio quality in mobile phone by managing voltage drops created by 217 Hz transients
- A practical approach to IP quality inspection
- Leveraging UVM based UFS Test Suite approach for Accelerated Functional Verification of JEDEC UFS IP
Latest Articles
- SoK: From Silicon to Netlist and Beyond Two Decades of Hardware Reverse Engineering Research
- An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks
- Enabling RISC-V Vector Code Generation in MLIR through Custom xDSL Lowerings
- A Scalable Open-Source QEC System with Sub-Microsecond Decoding-Feedback Latency
- SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks