How to manage a billion cycles
By Alain Raynaud, EVE
(02/12/08, 11:57:00 AM EST) -- EE Times
After years discussing verification strategies with hundreds of ASIC designers, it finally hit me: We're at the point where designers are trying to manage billions of cycles of simulation.
Take the video chip business where H.264 and high- definition TV are hot. These chip designers need to simulate hundreds of conformance streams to make sure that the chip is ready to ship. In the wireless handheld market, firmware is key. Ultimately, the device must boot Linux and run a Java application on its LCD screen. And, designers of network routers need to stress their chips through pseudo-random traffic to benchmark key performance metrics, such as packet drop rate.
All these tasks have one thing in common: they require billions of cycles of simulation. Until a designer realizes that he or she can't manage billions of cycles like any other simulation, they hit a wall that I call the "Billion-Cycle Challenge."
To read the full article, click here
Related Semiconductor IP
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- NPU IP Core for Mobile
Related White Papers
- Bluetooth to reach $4.4 billion chip potential in 2005, says report
- 10-Gbit Ethernet revenues to reach $3.6 billion by '04, says Dataquest
- System-on-chip market to hit 1.3 billion units in 2004, says new report
- How to manage a derivative SoC project
Latest White Papers
- QiMeng: Fully Automated Hardware and Software Design for Processor Chip
- RISC-V source class riscv_asm_program_gen, the brain behind assembly instruction generator
- Concealable physical unclonable functions using vertical NAND flash memory
- Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
- Transition Fixes in 3nm Multi-Voltage SoC Design