Design for Low-Power Manufacturing Test
By Chris Allsup, Synopsys, Inc.
March 18, 2008 -- edadesignline.com
The very process of testing digital circuits routinely increases their dynamic power consumption to levels far exceeding their power specification. If the power consumption is great enough, it can result in failures at wafer probe or pre-burn-in package test that require a significant amount of time and effort to debug. This issue, especially prevalent when testing very large systems-on-a-chip (SoCs) under corner conditions, causes unnecessary yield loss on the production line and ultimately reduces manufacturers' gross margins. The best way to avoid test power problems is to incorporate power-aware testing techniques in the design-for-test (DFT) process. In this article, we'll first examine the relationship between dynamic power consumption and test to determine why managing power is more critical today than ever before. Then we'll explore two distinct DFT methodologies that take advantage of recent advances in automatic test pattern generation (ATPG) technology to automate generation of low-power manufacturing tests.
To read the full article, click here
Related Semiconductor IP
- JESD204E Controller IP
- eUSB2V2.0 Controller + PHY IP
- I/O Library with LVDS in SkyWater 90nm
- 50G PON LDPC Encoder/Decoder
- UALink Controller
Related Articles
- The need to address power during manufacturing test
- Low power is everywhere
- An ESD efficient, Generic Low Power Wake up methodology in an SOC
- A need for static and dynamic Low Power Verification
Latest Articles
- Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT Security
- In-Pipeline Integration of Digital In-Memory-Computing into RISC-V Vector Architecture to Accelerate Deep Learning
- QMC: Efficient SLM Edge Inference via Outlier-Aware Quantization and Emergent Memories Co-Design
- ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design
- COVERT: Trojan Detection in COTS Hardware via Statistical Activation of Microarchitectural Events