Low power is everywhere
Mary Ann White, Synopsys
EETimes (4/18/2012 11:22 AM EDT)
Meeting power budgets for most System-on-Chip (SoC) designs today is no longer a requirement for mobile applications only. Almost every market segment today has some concern with designing in low power features—although the driving factor for why does differ among them. The primary impetus for low power design was initially driven by the mobile market due to the need for extending battery life; however, different segments do have different reasons for making power a primary design requirement.
For example, the advent of the internet and social media heavily drives the Servers and Networking Market segments where large server clouds and compute farms need to work reliably without overheating; so, their primary concern is reducing the amount of expensive energy required for operation and air conditioning. Other markets such as the multimedia and set top box segments are plugged into the wall but ‘green’ initiatives and the high cost of electricity have forced them into increasing energy efficiency through building in low power techniques similar to those used in the mobile application space.
Power is now a primary requirement for all designs – it’s not just about performance or area anymore and there are several factors that designers need to take into consideration to meet the stringent low power requirements. There are several key components that comprise a low power design and offer methods for controlling power:
- Technology process selection provides a power vs. performance vs. area tradeoff
- Architectural and implementation techniques offers power vs. complexity tradeoffs
- Optimization engines delivers on rapid time-to-market and quality of results
To read the full article, click here
Related Semiconductor IP
- Bluetooth Low Energy 6.0 Digital IP
- Ultra-low power high dynamic range image sensor
- Flash Memory LDPC Decoder IP Core
- SLM Signal Integrity Monitor
- Digital PUF IP
Related White Papers
- Low power design is here to stay
- An ESD efficient, Generic Low Power Wake up methodology in an SOC
- A need for static and dynamic Low Power Verification
- Low Power Design for Testability
Latest White Papers
- How Next-Gen Chips Are Unlocking RISC-V’s Customization Advantage
- Efficient Hardware-Assisted Heap Memory Safety for Embedded RISC-V Systems
- Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions
- How Mature-Technology ASICs Can Give You the Edge
- Exploring the Latest Innovations in MIPI D-PHY and MIPI C-PHY