Low power LDPC decoder created using high level synthesis
By Yang Sun and Joseph R. Cavallaro, Rice University, Houston, Texas, Tai Ly, Synfora Inc., Mountain View, Calif.
edadesignline.com (January 13, 2010)
Introduction
With the popularity of mobile wireless devices soaring, the wireless communication market continues to see rapid growth. However, with this growth comes a significant challenge. Many applications, such as digital video, need new high data rate wireless communication algorithms. The continuous evolution of these wireless specifications is constantly widening the gap between wireless algorithmic innovation and hardware implementation. In addition, low power consumption is now a critical design issue, since the life of a battery is a key differentiator among consumer mobile devices. The chip designer's most important task is to implement highly complex algorithms into hardware as quickly as possible, while still retaining power efficiency. High Level Synthesis (HLS) methodology has already been widely adopted as the best way to meet the challenge. This article gives an example in which an HLS tool is used, together with architectural innovation, to create a low power LDPC decoder.
To read the full article, click here
Related Semiconductor IP
- NavIC LDPC Decoder
- Flash Memory LDPC Decoder IP Core
- 1Gbit/s LDPC Decoder and Encoder (WiMedia UWB)
- CMMB LDPC decoder
- Gigabit-range, low complexity LDPC decoder
Related White Papers
- Testable SoCs : Test flow speeds up MP3 decoder development to eight weeks
- Improving Design Timing and Simplicity for Lower Cost and High Performance Multistandard Audio Decoder STA012
- H.264 decoder test takes careful planning
- IP Core for an H.264 Decoder SoC
Latest White Papers
- OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
- Balancing Power and Performance With Task Dependencies in Multi-Core Systems
- LLM Inference with Codebook-based Q4X Quantization using the Llama.cpp Framework on RISC-V Vector CPUs
- PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions
- Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS