H.264 decoder test takes careful planning
(08/21/2006 9:00 AM EDT), EETimes
The testing of advanced video decoders is a daunting task, considering the greater complexity and nonlinearity of H.264 compared with MPEG-2. Decoding depends on numerous contexts and states that one would be very unlikely to encounter through random interoperability testing.
For starters, context-adaptive binary arithmetic coding, one of the most important improvements in H.264, is also its most complex. Hundreds of context models must be tested for proper initialization, derivation and updating. Any error will produce an incorrect binarization of one or more syntax elements. Detailed, systematic tests are needed to cover the possible combinations. The results need to be clearly displayed and documented so that this complex decoding block can be debugged.
Less-sophisticated testing techniques involve decoding, capturing and comparing tens of thousands of frames of data against decoded references or checksums, whereas more advanced tools amplify and propagate results to a few verification screens. Unless the results are specifically amplified, most of the capture-and-compare test plans also fail when images are resized or sent through a display processor.
The easiest tools to use are those where the reference is built into the stream, giving a clear pass/fail verification screen for every test. Many of these streams even support visual verification, so that completed systems can be judged without having to attach probes or capture equipment.
To read the full article, click here
Related Semiconductor IP
- H.264 Decoder
- H.264 Encoder
- Scalable Ultra-High Throughput H.264 Encoder − Full Motion Estimation
- Scalable Ultra-High Throughput H.264 Encoder − Light Motion Estimation
- Scalable Ultra-High Throughput H.264 Encoder − Intra Frames (IDR) Encoding
Related White Papers
- Testable SoCs : Test flow speeds up MP3 decoder development to eight weeks
- Is Agile coming to Hardware Development?
- Efficient SIMD and Algorithmic Optimization Techniques for H264 Decoder on Cortex A9
- Test engineers must join ASIC flow early
Latest White Papers
- QiMeng: Fully Automated Hardware and Software Design for Processor Chip
- RISC-V source class riscv_asm_program_gen, the brain behind assembly instruction generator
- Concealable physical unclonable functions using vertical NAND flash memory
- Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
- Transition Fixes in 3nm Multi-Voltage SoC Design