Improving ASIP code generation and back-end compilation: Part 2
Wayne Wolf, Georgia Institute of Technology
Embedded.com (April 28, 2013)
Instruction selection becomes important when the processor has limited or irregular resources. Many DSPs have irregular register sets and operations, so instruction selection becomes very important for these machines. Limited or irregular processor resources are also influential when operations are performed. Instruction selection and scheduling may interact as a result of resource limitations.
As part of the FlexWare system, Liem et al. [7] developed an instructiongeneration system for ASIPs with irregular register files. Figure 3-8 shows the intermediate representation for programs, which includes both data and control flow aspects.
To read the full article, click here
Related Semiconductor IP
- RVA23, Multi-cluster, Hypervisor and Android
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- NPU IP Core for Mobile
- RISC-V AI Acceleration Platform - Scalable, standards-aligned soft chiplet IP
- H.264 Decoder
Related White Papers
- Paving the way for the next generation of audio codec for True Wireless Stereo (TWS) applications - PART 5 : Cutting time to market in a safe and timely manner
- Tips for efficient embedded code generation
- Advanced Topics in FinFET Back-End Layout, Analog Techniques, and Design Tools
- Paving the way for the next generation audio codec for the True Wireless Stereo (TWS) applications - PART 1 : TWS challenges explained
Latest White Papers
- QiMeng: Fully Automated Hardware and Software Design for Processor Chip
- RISC-V source class riscv_asm_program_gen, the brain behind assembly instruction generator
- Concealable physical unclonable functions using vertical NAND flash memory
- Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
- Transition Fixes in 3nm Multi-Voltage SoC Design