Time to exploit IDEs for hardware design and verification

Cristian Amitroaie, Amiq Consulting, Andrew Betts, an independent consultant
5/18/2011 10:26 AM EDT

Integrated Development Environments are solidly established in the software community. Eclipse, a major open source IDE, has been downloaded over 5 million times. Data published in 2008 by its rival, NetBeans, showed their IDE to be in use by over 2 million users worldwide. Commercial IDEs, such as Microsoft’s Visual Studio, are also popular.

The IDE’s advantages to software engineers are many, and most of them are relevant to engineers working on hardware verification. It is, after all, a software task. Languages used include C, C++ and SystemC, of course, but increasingly the dedicated verification languages e and SystemVerilog. Many aspects of hardware design are also language based, and can potentially benefit from the use of an IDE. Most digital designers use VHDL or Verilog, and Analog/Mixed-Signal (AMS) designers are increasingly taking up related languages such as VHDL-A and VerilogAMS.

By taking a closer look at the differences between the general software and the more specialized hardware verification communities, this article will attempt to explain the current growth and future prospects of IDEs in hardware verification. The implications for hardware design are also examined.

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