How to implement an open IP encryption flow

Today's extremely large and complex ASIC and FPGA designs use significant amounts of third-party intellectual property (IP). These IP blocks may represent general-purpose processor cores, digital signal processor (DSP) cores, memory controllers, communications functions, etc. Furthermore, this third-party IP, which may account for a large proportion of the overall design, often originates from a number of different IP vendors.

Not surprisingly, due to the fact that each IP block represents a considerable amount of time and investment, the IP vendors wish to guard their secrets. The way this is achieved is to encrypt the source, which means encoding it so as to make it unintelligible to unauthorized parties.

The problem is that, at the time of this writing, there is no standard for encryption and decryption in electronic design flows that facilitates industry-wide interoperability. As a result, different IP vendors and EDA vendors have employed a variety of proprietary schemes. In turn, this has resulted in a huge support burden on the various organizations, it is confusing to the end user, and it can result in a lack of consistency (simulating one version of the IP block and synthesizing a different version, for example).

In order to address this issue, the scientists and engineers at Synplicity have invented (and implemented) an open IP encryption environment that will facilitate the use of protected IP throughout the design flow: from IP vendor to EDA vendor to silicon vendor.

This paper first discusses where the various encryption and decryption steps occur in the design flow. Next, it introduces the conventional encryption techniques – specifically symmetric and asymmetric encryption algorithms – and explains the problems associated with these approaches in the context of an electronic design flow. Finally, a hybrid symmetric-asymmetric open solution is described that leverages existing technology, that fully addresses the needs of modern electronic design environments, and that would be easy to adopt by IP, EDA, and silicon vendors.

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