PRODUCT HOW-TO: Hardware IP design reuse made easy with Altium's Innovation Station
By Phil Loughhead, Altium Ltd.
Embedded.com (01/30/09, 09:43:00 PM EST)
The ability to reuse existing sections of designs is like the quest for the holy grail in our design team - something we value highly and dream of finding, but have yet to discover. And if you were to push me to take a position, I used to doubt it would ever be found.
So I'd have to say that I was skeptical when I read statements about design reuse in Altium Designer - "I'll believe that when I see it" were my exact words.
Everyone in the team was already practicing design re-use, we were copying and pasting sections of existing designs " like standard comms or power supply sub-circuits " into our current projects.
But there was no integrity in the copied design, because any number of mistakes could be made during the copy/paste process, and the engineer could and would modify the circuit to suit their idea of a good circuit. That meant it had to be subject to the standard review and triple-check sign-off process.
Embedded.com (01/30/09, 09:43:00 PM EST)
The ability to reuse existing sections of designs is like the quest for the holy grail in our design team - something we value highly and dream of finding, but have yet to discover. And if you were to push me to take a position, I used to doubt it would ever be found.
So I'd have to say that I was skeptical when I read statements about design reuse in Altium Designer - "I'll believe that when I see it" were my exact words.
Everyone in the team was already practicing design re-use, we were copying and pasting sections of existing designs " like standard comms or power supply sub-circuits " into our current projects.
But there was no integrity in the copied design, because any number of mistakes could be made during the copy/paste process, and the engineer could and would modify the circuit to suit their idea of a good circuit. That meant it had to be subject to the standard review and triple-check sign-off process.
To read the full article, click here
Related Semiconductor IP
- eUSB2V2.0 Controller + PHY IP
- I/O Library with LVDS in SkyWater 90nm
- 50G PON LDPC Encoder/Decoder
- UALink Controller
- RISC-V Debug & Trace IP
Related Articles
- The Growing Imperative Of Hardware Security Assurance In IP And SoC Design
- Formal-based methodology cuts digital design IP verification time
- VLSI Physical Design Methodology for ASIC Development with a Flavor of IP Hardening
- Low Power Design in SoC Using Arm IP
Latest Articles
- COVERT: Trojan Detection in COTS Hardware via Statistical Activation of Microarchitectural Events
- A Reconfigurable Framework for AI-FPGA Agent Integration and Acceleration
- Veri-Sure: A Contract-Aware Multi-Agent Framework with Temporal Tracing and Formal Verification for Correct RTL Code Generation
- FlexLLM: Composable HLS Library for Flexible Hybrid LLM Accelerator Design
- Secure Multi-Path Routing with All-or-Nothing Transform for Network-on-Chip Architectures