FPGAs unleash potential of Flash memory for enterprise applications
David McIntyre, Altera Corporation
EETimes (3/16/2012 10:00 AM EDT)
Enterprise storage subsystems today are undergoing an essential transformation. The sheer volume of enterprise data and transactions is increasing by as much as 50-60% per year. The rapid proliferation of cloud computing and virtualization as a means to more efficiently manage these burgeoning data workloads has spawned explosive growth in the number and size of data centers. Along with the exponential growth in enterprise storage comes an imperative to improve memory subsystem performance capacity and value.
System administrators are finding that conventional storage architectures, which rely heavily on hard disk media, lack the performance to meet the demands of today’s workloads. Application architects are responding by adopting a holistic approach to memory architecture that combines conventional storage media with a new entrant in the enterprise space, flash memory. Long a preferred memory medium for consumer devices, NAND flash memory offers 10-100X performance improvement over that of hard disk drives (HDDs) for enterprise applications. Flash is also the most cost-effective non-volatile storage medium for frequently used data and applications. By using flash memory arrays, enterprises can dramatically reduce storage footprint, CPU and software licenses, and consequently, data center power, space and operation cost.
To read the full article, click here
Related Semiconductor IP
- SATA Host on Altera Arria II GX
- SATA Device Controller on Altera Arria II GX
- Aurora-like 8b/10b @3Gbps for ALTERA Devices
- Aurora-like 64b/66b @14Gbps for ALTERA Devices
- eCPRI Altera® FPGA IP
Related White Papers
- Selection of FPGAs and GPUs for AI Based Applications
- LPDDR flash: A memory optimized for automotive systems
- Maximizing Performance & Reliability for Flash Applications with Synopsys xSPI Solution
- Understanding the contenders for the Flash memory crown
Latest White Papers
- DRsam: Detection of Fault-Based Microarchitectural Side-Channel Attacks in RISC-V Using Statistical Preprocessing and Association Rule Mining
- ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors
- Practical Considerations of LDPC Decoder Design in Communications Systems
- A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems
- A logically correct SoC design isn’t an optimized design