FPGA Debug in the Modern World
Joe Mallett, Synopsys
EETimes (4/11/2016 01:20 PM EDT)
A versatile, iterative, and incremental debug methodology allows FPGA designers to deliver debugged designs quickly and easily ensuring design integrity and robustness.
FPGA device density is continuing to grow at approximately 2x per node, which is driving the ability for FPGAs to incorporate more of the system design into the devices. This means that companies designing new FPGA-based products continue to drive higher integration and, subsequently, more complexity into their system designs. This has led companies designing complex FPGAs to move increasingly toward licensing IP cores for the majority of the building blocks of their designs, as opposed to building their own in-house custom versions.
FPGA designers typically use IP from multiple sources ranging from internal to FPGA device vendors. In order to efficiently leverage IP from multiple sources, designers require synthesis and debug tools that support the portability of IP across technologies, along with the ability to properly handle the various forms of IP. The Synplify synthesis tools automate much of the handling of design IP by directly supporting vendor IP catalogs like Altera's Megawizards and Xilinx's IP catalog.
To read the full article, click here
Related Semiconductor IP
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- USB 20Gbps Device Controller
- SM4 Cipher Engine
- Ultra-High-Speed Time-Interleaved 7-bit 64GSPS ADC on 3nm
- Fault Tolerant DDR2/DDR3/DDR4 Memory controller
Related White Papers
- FPGA Prototyping of Complex SoCs: RTL code migration and debug strategies
- Using Multi-Gigabit Transceivers to Test and Debug FPGA
- Tackling large-scale SoC and FPGA prototyping debug challenges
- FPGA debugging techniques to speed up pre-silicon validation
Latest White Papers
- Fault Injection in On-Chip Interconnects: A Comparative Study of Wishbone, AXI-Lite, and AXI
- eFPGA – Hidden Engine of Tomorrow’s High-Frequency Trading Systems
- aTENNuate: Optimized Real-time Speech Enhancement with Deep SSMs on RawAudio
- Combating the Memory Walls: Optimization Pathways for Long-Context Agentic LLM Inference
- Hardware Acceleration of Kolmogorov-Arnold Network (KAN) in Large-Scale Systems