Embedded FPGAs seen surging
Embedded FPGAs seen surging
By George Leopold, EE Times
January 13, 2003 (11:49 a.m. EST)
URL: http://www.eetimes.com/story/OEG20030113S0023
SCOTTSDALE, Ariz. -- The nascent embedded FPGA market should remain immune to the impact of the recent semiconductor industry slide while continuing to attract investment, a market reseacher said. In-Stat/MDR reported in a study released Monday (Jan.13) that embedded FPGA technology remains in the early stages of development and is thus more likely to survive the downturn seen in other market segments like DRAMs. The situation has been aided by continuing strong investment in technology development, the market researcher found. Citing IBM Corp.'s recent licensing of Xilinx's SRAM-based FPGA core, In-Stat analyst Jerry Worchel concluded that “embedded FPGA technology will be well on its way to recovery and growth” by the first part of 2003. The market for cell-based designs containing blocks of embedded FPGAs is forecast to reach more than $600 million by 2006, the researchers said. That means compound annual growth rates during the period co uld top 190 percent. Communications applications could lead the way, especially for networking and telecommunications infrastructure applications. Moreover, the researcher forecast that the flash architecture could dominate consumption of embedded FPGAs. The SRAM approach could also gain ground, Worchel added.
Related Semiconductor IP
- HBM4 PHY IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
- HBM4 Controller IP
- IPSEC AES-256-GCM (Standalone IPsec)
Related Articles
- How FPGAs, multicore CPUs, and graphical programming are changing embedded design
- Microcontroller Architects Look to Embedded FPGAs for Flexibility
- Considerations Regarding Benchmarking eFPGAs (Embedded FPGAs)
- How embedded FPGAs fit AI applications
Latest Articles
- ElfCore: A 28nm Neural Processor Enabling Dynamic Structured Sparse Training and Online Self-Supervised Learning with Activity-Dependent Weight Update
- A 14ns-Latency 9Gb/s 0.44mm² 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX
- Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor
- Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing
- Leveraging FPGAs for Homomorphic Matrix-Vector Multiplication in Oblivious Message Retrieval