Designing hardware with C-based languages

Venkat Krishnaswamy, Calypto Design Systems
EE Times
11/14/2005 10:00 AM EST
 
With increasing design complexity and shortening time-to-market, hardware designers have sought to use higher levels of abstraction for both verification and design. For many hardware engineers, C-based languages (C/C++ or SystemC) have become a means to specify designs for verification, in addition to offering a starting point for implementation.

The process of design starts with a transactional model that is used mostly for architectural exploration. This transactional model may be refined into a more-detailed C specification model for use in verification. Alternatively, the performance verification model may have sufficient detail for use as a "golden" model for verification. This model is then labeled the specification model. It can be used as a baseline for generating RTL (using behavioral synthesis) or for verifying manually written RTL.

As designers increasingly use this process, their success depends on the availability of a sound methodology and a set of guidelines for coding an effective specification model. Such a model should achieve high simulation speed for model validation; achieve the ability to modify the design easily as the project progresses; be an effective specification model for behavioral synthesis flows; and be an effective specification model for formal verification, so that both hand-coded RTL and behavioral synthesis output can be accommodated.

To ensure a faster path to success when designing hardware with C-based languages, here is a short list of items that require attention.

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