CoreMark: A realistic way to benchmark CPU performance
Shay Gal-On and Markus Levy, EEMBC
1/31/2011 3:00 PM EST
Many attempts have been made to provide a single number that can totally quantify the ability of a CPU. Be it MHz, MOPS, MFLOPS—all are simple to derive but misleading when looking at actual performance potential. Dhrystone was the first attempt to tie a performance indicator, namely DMIPS, to execution of real code—a good attempt that has long served the industry but is no longer meaningful. BogoMIPS attempts to measure how fast a CPU can do nothing, for what that's worth.
The need still exists for a simple and standardized benchmark that provides meaningful information about the CPU core. Introducing CoreMark, available for free download from www.coremark.org. CoreMark ties a performance indicator to execution of simple code, but rather than being entirely arbitrary and synthetic, the code for the benchmark uses basic data structures and algorithms that are common in practically any application. Furthermore, in developing this benchmark, the Embedded Microprocessor Benchmark Consortium (EEMBC) carefully chose the CoreMark implementation such that all computations are driven by run-time–provided values to prevent code elimination during compile-time optimization. CoreMark also sets specific rules about how to run the code and report results, thereby eliminating inconsistencies.
To read the full article, click here
Related Semiconductor IP
- Multi-channel Ultra Ethernet TSS Transform Engine
- Configurable CPU tailored precisely to your needs
- Ultra high-performance low-power ADC
- HiFi iQ DSP
- CXL 4 Verification IP
Related Articles
- Overcoming the embedded CPU performance wall
- ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design
- Optimizing High Performance CPUs, GPUs and DSPs? Use logic and memory IP - Part II
- Reconfiguring Design -> How to extend configurable CPU performance
Latest Articles
- GenAI for Systems: Recurring Challenges and Design Principles from Software to Silicon
- Creating a Frequency Plan for a System using a PLL
- RISCover: Automatic Discovery of User-exploitable Architectural Security Vulnerabilities in Closed-Source RISC-V CPUs
- MING: An Automated CNN-to-Edge MLIR HLS framework
- Fault Tolerant Design of IGZO-based Binary Search ADCs