Configure, Confirm, Ship: Build Secure Processor-Based Systems with Faster Time-to-Market
By Synopsys
Security is a first-order design requirement for processor-based systems. Processor designers implement security functionality directly into the hardware itself to protect the system at its most fundamental layer. System integrators that use processor IP such as Synopsys’ DesignWare® ARC® processors must ensure that they configure and manage the protection and security features correctly, and that they do not introduce vulnerabilities. Evaluating the security of complex, highly combined hardware-software systems and ensuring these systems are free from vulnerabilities is hard. In this white paper, we show how Tortuga Logic’s Radix-S security verification platform with Synopsys’ ARC Processor IP offer a powerful solution for this complex problem. We demonstrate the combined hardware-software security verification by creating an example system comprised of the ARC processor IP and vulnerable software that configures the memory protection unit incorrectly. With the additional capabilities provided by Radix-S, we quickly identify the flaw using pre-existing functional verification infrastructure. Furthermore, we show how system integrators can verify the security of protected debug logic with this technology.
To read the full article, click here
Related Semiconductor IP
- JPEG XL Encoder
- LPDDR6/5X/5 PHY V2 - Intel 18A-P
- ML-KEM Key Encapsulation & ML-DSA Digital Signature Engine
- MIPI SoundWire I3S Peripheral IP
- ML-DSA Digital Signature Engine
Related Articles
- Stitch and ship no longer viable
- Achieving Better Productivity with Faster Synthesis
- Implementing Ultra Low Latency Data Center Services with Programmable Logic
- Secure updates for FPGA-based systems
Latest Articles
- CircuitGuard: Mitigating LLM Memorization in RTL Code Generation Against IP Leakage
- FPGA-Accelerated RISC-V ISA Extensions for Efficient Neural Network Inference on Edge Devices
- MultiVic: A Time-Predictable RISC-V Multi-Core Processor Optimized for Neural Network Inference
- AnaFlow: Agentic LLM-based Workflow for Reasoning-Driven Explainable and Sample-Efficient Analog Circuit Sizing
- FeNN-DMA: A RISC-V SoC for SNN acceleration