Commentary: SystemVerilog enables design with verification
(06/26/2007 12:35 PM EDT)
The SystemVerilog language standard is one of the hottest topics in EDA today, and with good reason. It takes a huge step up from traditional hardware description languages, incorporating key concepts from proven verification languages, property/assertion languages, and even object-oriented programming languages. With its many new features, SystemVerilog can appear a bit daunting in its entirety.
Partly for that reason, and partly because of the history of the donations that influenced the standard, it is common to divide the new features of SystemVerilog into three categories: assertion constructs, design constructs and verification constructs. This categorization has some merit, at least from a syntax perspective, but it can be misleading, in that logic designers use more than the design constructs, and verification engineers use more than the verification constructs.
To read the full article, click here
Related Semiconductor IP
- Flexible Pixel Processor Video IP
- Bluetooth Low Energy 6.0 Digital IP
- Verification IP for Ultra Ethernet (UEC)
- MIPI SWI3S Manager Core IP
- Ultra-low power high dynamic range image sensor
Related White Papers
- Design patterns in SystemVerilog OOP for UVM verification
- Modeling and Verification of Mixed Signal IP using SystemVerilog in Virtuoso and NCsim
- Design & Verify Virtual Platform with reusable TLM 2.0
- Implementing Parallel Processing and Fine Control in Design Verification
Latest White Papers
- Security Enclave Architecture for Heterogeneous Security Primitives for Supply-Chain Attacks
- relOBI: A Reliable Low-latency Interconnect for Tightly-Coupled On-chip Communication
- Enabling Space-Grade AI/ML with RISC-V: A Fully European Stack for Autonomous Missions
- CANDoSA: A Hardware Performance Counter-Based Intrusion Detection System for DoS Attacks on Automotive CAN bus
- How Next-Gen Chips Are Unlocking RISC-V’s Customization Advantage