Cache-Coherence Verification
Rajeev Ranjan, CTO, Jasper Design Automation
8/17/2011 11:38 AM EDT
As consumers, we place many demands on our personal electronics, especially mobile devices. We want them to perform all sorts of tasks efficiently, accurately, and with minimal power consumption. Complex embedded SoCs have largely enabled the functional capabilities of these devices. To ensure that these devices perform at a desired level to accomplish the tasks needed, today’s embedded SoCs must consist of high-performance, heterogeneous, and multi-processing agents. The presence of a large number of data processing agents sharing a memory resource on an SoC requires that the agents maintain some type of locally cached data to reduce the data transportation cost. This, in turn, leads to the requirement for cache coherency to allow agents to cache data during processing and then make it available to the next processing agent.
To read the full article, click here
Related Semiconductor IP
- Flexible Pixel Processor Video IP
- Bluetooth Low Energy 6.0 Digital IP
- MIPI SWI3S Manager Core IP
- Ultra-low power high dynamic range image sensor
- Neural Video Processor IP
Related White Papers
- Verification care abouts for SoC internal channel characterization using an ADC
- Verification challenges of ADC subsystem integration within an SoC
- Can Hardware-Assisted Verification Save SoC Realization Time?
- Formal, simulation, and AMBA verification IP combine to verify configurable powerline networking SoC
Latest White Papers
- Enabling Space-Grade AI/ML with RISC-V: A Fully European Stack for Autonomous Missions
- CANDoSA: A Hardware Performance Counter-Based Intrusion Detection System for DoS Attacks on Automotive CAN bus
- How Next-Gen Chips Are Unlocking RISC-V’s Customization Advantage
- Efficient Hardware-Assisted Heap Memory Safety for Embedded RISC-V Systems
- Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions