Broadcast video infrastructure implementation using FPGAs
Tam Do, Senior Technical Marketing Manager, Broadcast/Consumer Applications Business Unit, Altera
Jun 07, 2006 (2:00 PM), CommsDesign
Introduction
The proliferation of high-definition television (HDTV) video content creation and the method of delivering these contents in a bandwidth-limited broadcast channel environment have driven new video compression standards and associated video image processing applications. Traditionally, only cable and satellite operators provided video delivery. Now telecommunication companies (telcos) are getting into this arena by using the latest video coder/decoders (CODECs) and video-processing technology to transmit digital video to the consumer via Internet protocol television (IPTV).
To read the full article, click here
Related Semiconductor IP
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
- UA Link DL IP core
- 10-bit Pipeline ADC - Tower 180 nm
- NoC Verification IP
- Simulation VIP for Ethernet UEC
Related Articles
- Emerging H.264 standard supports broadcast video encoding
- Automated video algorithm implementation
- Video and image processing design using FPGAs
- Polyphase Video Scaling in FPGAs
Latest Articles
- Analog Foundation Models
- Modeling and Optimizing Performance Bottlenecks for Neuromorphic Accelerators
- RISC-V Based TinyML Accelerator for Depthwise Separable Convolutions in Edge AI
- Exclude Smart in Functional Coverage
- A 0.32 mm² 100 Mb/s 223 mW ASIC in 22FDX for Joint Jammer Mitigation, Channel Estimation, and SIMO Data Detection