Video and image processing design using FPGAs
January 12, 2007 -- videsignline.com
FPGAs eliminate the up-front non-recurring engineering costs and minimum order quantities associated with ASICs, and the costly risks of multiple silicon iterations through the capability to be reprogrammed as needed during the design process.
Innovations such as HDTV and digital cinema revolve around video and image processing and the rapid evolution of video technology. Major advances in image capture and display resolutions, advanced compression techniques, and video intelligence are the driving forces behind these technological innovations. At the same time, rapid change in standards and higher resolutions are pushing designers away from off-the-shelf technology.
Resolutions in particular have increased dramatically in just the last few years. The following table illustrates current state-of-the-art resolutions in different end types of applications.
Table 1: Resolutions by Application Types
The move from standard definition (SD) to high definition (HD) represents a 6X increase in data needing to be processed. Video surveillance is also moving from the Common Intermediate Format (CIF) (352 x 288) to the D1 format (704 x 576) as a standard requirement, with some industrial cameras even moving to HD at 1280 x 720. Military surveillance, medical imaging, and machine vision applications are also moving to very high resolution images.
Related Semiconductor IP
- Sine Wave Frequency Generator
- CAN XL Verification IP
- Rad-Hard GPIO, ODIO & LVDS in SkyWater 90nm
- 1.22V/1uA Reference voltage and current source
- 1.2V SLVS Transceiver in UMC 110nm
Related White Papers
- Using vector processing for HD video scaling, de-interlacing, and image customization
- Video and image processing design using FPGAs
- Implementing digital processing for automotive radar using SoC FPGAs
- Designing low-power video image stabilization IP for FPGAs
Latest White Papers
- OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
- Balancing Power and Performance With Task Dependencies in Multi-Core Systems
- LLM Inference with Codebook-based Q4X Quantization using the Llama.cpp Framework on RISC-V Vector CPUs
- PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions
- Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS