Assertion-based verification in mixed-signal design

Prabal Bhattacharya and Don O'Riordan
10/17/2011 12:01 PM EDT

Introduction

Assertion-based verification (ABV) is a powerful verification approach that has been proven to help digital IC architects, designers, and verification engineers improve design quality and reduce time to market. But ABV has rarely been applied to analog/mixed-signal verification. This article looks at challenges in analog/mixed-signal verification, evaluates how the ABV concept can address some of those challenges, and shows how languages such as Property Specification Language (PSL) and SystemVerilog Assertions (SVA) can be used to write complex analog/mixed-signal assertions.

Assertions, by definition, capture the intended behavior of a design. In verification terminology, ABV can be positioned both as a white-box and a black-box approach in that the user can create properties (or asserted behaviors) that can monitor the design deep within the hierarchy, reaching the internals of the design blocks as well as the interfaces of the design blocks.

Assertions are written both during development of the design and the verification environment. Both designers and verification engineers can consequently be involved in identifying requirements and capturing them as assertions.

So where do mixed-signal assertions fit in?

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