Agile Design for Hardware, Part II
David Patterson and Borivoje NikoliÄ, UC Berkeley
EETimes (7/30/2015 07:00 AM EDT)
In the second of a three-part series, two Berkeley professors suggest its time to apply Agile design techniques to hardware.
We asked readers of Part I to guess the cost of a prototype run of 28 nm chips, as Agile development relies on a sequence of interim prototypes versus the One Big Tapeout of the traditional Waterfall process. Here are the results:
The surprisingly low manufacturing cost of prototype chips—one fifth the readers’ estimate—means Agile development is eminently affordable, even for academics. (See www.AgileSoC.com for more evidence.) It also calls into question the current high cost of designing SoCs using the Waterfall process. Having established Agile’s viability, based on our experience we propose four guidelines to lower development costs.
To read the full article, click here
Related Semiconductor IP
- HBM4 PHY IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
- HBM4 Controller IP
- IPSEC AES-256-GCM (Standalone IPsec)
Related Articles
- Agile Design for Hardware, Part I
- How to design secure SoCs, Part II: Key Management
- QiMeng: Fully Automated Hardware and Software Design for Processor Chip
- How to design secure SoCs, Part III: Secure Boot
Latest Articles
- A 14ns-Latency 9Gb/s 0.44mm² 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX
- Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor
- Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing
- Leveraging FPGAs for Homomorphic Matrix-Vector Multiplication in Oblivious Message Retrieval
- Extending and Accelerating Inner Product Masking with Fault Detection via Instruction Set Extension