Agile Design for Hardware, Part II
David Patterson and Borivoje NikoliÄ, UC Berkeley
EETimes (7/30/2015 07:00 AM EDT)
In the second of a three-part series, two Berkeley professors suggest its time to apply Agile design techniques to hardware.
We asked readers of Part I to guess the cost of a prototype run of 28 nm chips, as Agile development relies on a sequence of interim prototypes versus the One Big Tapeout of the traditional Waterfall process. Here are the results:
The surprisingly low manufacturing cost of prototype chips—one fifth the readers’ estimate—means Agile development is eminently affordable, even for academics. (See www.AgileSoC.com for more evidence.) It also calls into question the current high cost of designing SoCs using the Waterfall process. Having established Agile’s viability, based on our experience we propose four guidelines to lower development costs.
To read the full article, click here
Related Semiconductor IP
- LPDDR6/5X/5 PHY V2 - Intel 18A-P
- MIPI SoundWire I3S Peripheral IP
- P1619 / 802.1ae (MACSec) GCM/XTS/CBC-AES Core
- LPDDR6/5X/5 Controller IP
- Post-Quantum ML-KEM IP Core
Related White Papers
- Agile Design for Hardware, Part I
- How to design secure SoCs, Part II: Key Management
- QiMeng: Fully Automated Hardware and Software Design for Processor Chip
- How to design secure SoCs, Part III: Secure Boot
Latest White Papers
- Multimodal Chip Physical Design Engineer Assistant
- Attack on a PUF-based Secure Binary Neural Network
- BBOPlace-Bench: Benchmarking Black-Box Optimization for Chip Placement
- FD-SOI: A Cyber-Resilient Substrate Against Laser Fault Injection—The Future Platform for Secure Automotive Electronics
- In-DRAM True Random Number Generation Using Simultaneous Multiple-Row Activation: An Experimental Study of Real DRAM Chips