A Case Study - RF ASIC Validation of a satellite transceiver
Maeve Colbert , IC Design Engineer , Semiconductor Solutions, S3 Group
EDN (May 27, 2015)
1. Abstract
ASIC validation in the RF world comes with its own set of hurdles and challenges, with high quality lab equipment, experience and know-how essential. A recently completed RF sub-system validation at S3 Group is presented in the form of a case study of the execution. The validation PCB design focused on impedance matching and shielding RF signals from noise sources. We built up an efficient, automated test harness based on LabVIEW, MATLAB and python. This unified test framework facilitated instrument set-up, test-case running, data collection, traceability, plotting of measurements, waveform generation and analysis.
2. Planning for Validation
This is a case study of the validation of a complex RF subsystem, carried out by S3 Group. It suggests some best practices and approaches to adopt.
A specialized S3 Group ASIC RF development team designed a complex satellite transceiver, for use in handsets (phones) and modems. Die samples were fabricated in three lots (Best, Typical and Worst Case) by TSMC in a 0.18µm RF CMOS process, which were packaged and tested. Approximately 100 of these samples were used to validate the IC design’s functionality and performance.
To read the full article, click here
Related Semiconductor IP
- ReRAM NVM in DB HiTek 130nm BCD
- UFS 5.0 Host Controller IP
- PDM Receiver/PDM-to-PCM Converter
- Voltage and Temperature Sensor with integrated ADC - GlobalFoundries® 22FDX®
- 8MHz / 40MHz Pierce Oscillator - X-FAB XT018-0.18µm
Related Articles
- Fault Injection in On-Chip Interconnects: A Comparative Study of Wishbone, AXI-Lite, and AXI
- From Principles to Practice: A Systematic Study of LLM Serving on Multi-core NPUs
- Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor
- UPF Constraint coding for SoC - A Case Study
Latest Articles
- An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks
- Enabling RISC-V Vector Code Generation in MLIR through Custom xDSL Lowerings
- A Scalable Open-Source QEC System with Sub-Microsecond Decoding-Feedback Latency
- SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks
- An FPGA Implementation of Displacement Vector Search for Intra Pattern Copy in JPEG XS