Buffer design for reducing Hold violations & IR drop
February 17, 2015
Semiconductor IP Articles Archive - Page 55 of 226
Sequential clock gating maximizes power savings at IP level
February 11, 2015
Non-Power-of-Two FFT Circuit Designs Do Not Have to be Difficult
February 9, 2015
Distribution: An approach for Virtual Platform scalability
February 2, 2015
Efficient Buffer design for Hold fixing
February 2, 2015
Modern Design Tools Facilitate Tuning DDR4 Signal Paths
January 27, 2015
Setup/hold interdependence in the pulsed latch (Spinner cell)
January 26, 2015
USB 3.1 Links Pose Challenges
January 22, 2015
An MLC ROM With Inserted Redundancy and Novel Sensing Scheme
January 19, 2015
Pitfalls for Logical Equivalence Check
January 19, 2015
Automatic ASIC-to-FPGA Conversion
January 16, 2015
Choosing the Best High-Speed ADC for Your SoC
January 12, 2015
Securing the IoT: Part 2 - Secure boot as root of trust
January 12, 2015
Securing the IoT: Part 1 - Public key cryptography
January 12, 2015
Optimizing data memory utilization
January 12, 2015
Implement a VXLAN-based network into an SoC
January 9, 2015
Bridging the gap between speed and power in Asynchronous SRAMs
January 6, 2015
A High Density, High Performance, Low Power Level Shifter
January 5, 2015
Dealing with memory access ordering in complex embedded designs
January 5, 2015
Sub-Threshold Design - A Revolutionary Approach to Eliminating Power
December 29, 2014
