Dynamic Margining: The Minima Approach to Near-threshold Design By Minima Processor November 30, 2017
IPs for automotive application - Functional Safety and Reliability By Priyank Shukla, Insilico November 27, 2017
Resolution of Interoperability challenges in Automatic Test Point insertion across different EDA vendors By Dr. Satish Chandra Tiwari, Sankalp Semiconductor November 27, 2017
Overcoming Timing Closure Issues in Wide Interface DDR, HBM and ONFI Subsystems By Brian Gardner, True Circuits November 13, 2017
Platform Software Verification Framework Solution for Safety Critical Systems By Nirav S Patel, eInfochips October 23, 2017
Smart Tracking of SoC Verification Progress Using Synopsys' Hierarchical Verification Plan (HVP) By Kishan Kalavadiya, eInfochips October 9, 2017
Combining USB Type-C and DisplayPort support in portable implementations By Morten Christiansen, Synopsys October 9, 2017
What's The Best Way to Verify Your SSD Controller? By Jean-Marie Brunet, Mentor, a Siemens Business October 5, 2017
Power Management for Internet of Things (IoT) System on a Chip (SoC) Development By Stephen M. Nolan, Vidatronic, Inc. September 18, 2017
Reduce Time to Market for FPGA-Based Communication and Datacenter Applications By Joe Mallet, Synopsys September 14, 2017
The case for integrating FPGA fabrics with CPU architectures By Alok Sanghavi, Achronix Semiconductor August 28, 2017
Processor-In-Loop Simulation: Embedded Software Verification & Validation In Model Based Development By Mangesh Kale, eInfochips August 28, 2017