Achieving higher performance in a multicore-based packet processing engine design
January 2, 2008
Semiconductor IP Articles
Efficient testbench implementation for verification proposed by Synopsys staffer
December 21, 2007
Do the Math: Reduce Cost and Get the Right Communications System I/O Connectivity
December 20, 2007
The role of secure memory in a trusted execution environment
December 20, 2007
Low Power Transport Demultiplexer for ATSC and DVB Broadcast Format
December 17, 2007
Lower the cost of intelligent power control with FPGAs
December 17, 2007
Achieving Yield in the Nanometer Age
December 17, 2007
Designing DDR3 SDRAM controllers with today's FPGAs
December 13, 2007
Combining C code with assembly code in DSP applications
December 13, 2007
Staged Scenario Generation For SoC Verification
December 10, 2007
Applying Constrained-Random Verification to Microprocessors
December 10, 2007
A revolution in functional verification
December 6, 2007
Case study of a complex video system-on-chip
December 3, 2007
Leveraging system models for RTL functional verification
December 3, 2007
Efficient radix-4 FFT on StarCore SC3000 DSPs
December 3, 2007
Embedded DSP Software Design Using Multicore a System-on-a-Chip (SoC) Architecture: Part 2
November 29, 2007
Viewpoint: Embrace platform-based design
November 29, 2007
Pushing the Frontier in Managing Power in Embedded ASIC or SoC Design with PCI Express
November 26, 2007
Using the ARM Cortex-R4 for DSP, part 2: Software optimization
November 26, 2007
Using the ARM Cortex-R4 for DSP, part 1: Benchmarks
November 19, 2007