Testable SoCs : Every new design is an ESD test chip

Every new design is an ESD test chip
By Brenda McCaffrey, CEO, White Mountain Labs, LLC, Phoenix, Ariz., EE Times
July 18, 2002 (11:21 a.m. EST)
URL: http://www.eetimes.com/story/OEG20020718S0024

The effect of low ESD immunity on a new product introduction can be both obvious and subtle. Manufacturing and test facilities adhere to ANSI standards for ESD protection and handling of chips based on minimum IC ESD immunity requirements. Facilities flooded with chips that require special ESD handling increase costs and cycle time. Yield suffers and customer deliveries may be affected. This scenario is especially worrisome to engineers who are dependent upon outsourced manufacturing.

Similarly, companies purchasing ICs have ESD immunity requirements based on their own manufacturing capabilities. Competitive advantage goes to the IC supplier who can deliver the most robust design.

Today, we see low and high pin-count products of amazing complexity as we move into SoC strategies. Although high pin-count products with over 500 leads are primarily digital circuits with straightforward chip floor planning, we are seeing significan t analog circuitry on board as well. The high pin-count mixed signal designs use innovative methods for isolating the analog and digital sections to improve parametric performance, thereby introducing ESD sensitivities.

There is an obvious need to determine ESD immunity in all ICs, but some of the biggest challenges are showing up in low pin-count designs with less than 200 leads that employ advanced RF and optical circuitry. Because of impedance matching concerns, conventional ESD protection structures cannot be used in these applications. It is common for engineering samples of new RF and optical products to omit ESD protection structures altogether. The advanced device and circuit designers are on the cutting edge of ESD protection development. As these technologies become incorporated into larger integrated system blocks, the problems will multiply.

In addition, we are dealing with new process technologies such as compound semiconductor materials, micro-electromechanical machined de vices and SOI. It is not uncommon for a company to design the same chip using radically different materials and fabrication processes, increasing the risk of introducing an unexpected ESD sensitivities.

By focusing all ESD protection development efforts on device-level protection circuits, the chip-level paths are often neglected. ESD events are notoriously difficult to simulate; test chips burn time and money, and do not address power bussing issues; design rules are meant to be broken; and innovation often occurs at the expense of manufacturability. Therefore, whether we admit it or not, every new product really becomes an ESD test chip. How much time-to-market does that cost?

This is a difficult problem to solve. The long-term solution lies in improved technology: models, simulation, and characterization. The short-term solution is strategic. Each engineer making decisions in the new product development cycle, needs to become familiar with the standard methods of ESD testing. A d evice designer may understand nuances of the breakdown characteristics of an ESD protection structure, but may not understand the details of the product-level testing that the device must withstand. The system designer may follow strict rules in the application of ESD protection cells to the chip-level design, but without knowledge of how the product will be zapped, t may not have the ability to adapt to the unique requirements of their chip architecture.

Approaching ESD as a top-down, system design issue rather than relying on design rule checks, is the only way to prevent ESD problems. In the ideal world of ESD protection, we like to imagine an ideal ESD protection structure that will be effective for any technology and circuit. Perhaps you have such a structure or cell. Even if you do, you may still fail your ESD immunity goals because of a lack of knowledge of ESD charac terization methods and industry standards.

The JEDEC and ESD Association standards for Human Body Model (HBM) and Machine Model (MM) are product-level tests that are designed to exercise all prominent charge paths through the pad cells to ground. Charged Device Model (CDM) simulates a situation in a manufacturing environment where the IC is tribo-electrically charged in a handler, for example, and then discharged upon contact with a grounded surface. Each model may result in a different failure mechanism within the IC. At a minimum, both HBM and CDM testing should be performed in order to understand the susceptibility of the IC to real-world electrostatic discharges. Machine Model (MM) testing is often used to characterize products such as RF circuits that are particularly sensitive to electrostatic discharges with fast rise times.

ESD test specifications and procedures are readily available through the Internet. Excellent sources of information include the JEDEC (www.jedec.org/) and E SD Association (www.esda.org/ Web sites.

A single question asked during the new product definition stage can make a big difference: "What is our plan for reaching acceptable ESD immunity levels in the industry standard ESD tests?" The answer must include not only proven ESD protection structures on individual pad cells, but must also address chip floor-planning, supply bussing, rule checks, and ESD test goals based on an understanding of the JEDEC or ESD Association methods.

ESD immunity encompasses the full spectrum of new product development issues, from semiconductor processes through top-level chip floor planning. Everyone in the new product development path should be aware of how his or her decisions affect the final ESD performance of the product.