Optimizing performance, power, and area in SoC designs using MIPS multi-threaded processors

Delfin Rodillas, MIPS Technologies
EETimes (4/4/2012 10:17 AM EDT)

Abstract

Hardware-based multi-threading technology has for some time been known in the industry as a feasible technique for improving system performance, but not too many people are aware of just how much traction the technology has gained since its early implementations in the 1960s.  This article provides a brief history of hardware based multi-threading and some examples of its commercial adoption so far.  It then gives an overview of the fundamental value of multi-threading in hardware, and describes MIPS Technologies’ multi-threading architecture and product offerings.  The article also provides several multi-threaded application examples—including those in the areas of driver assistance systems and home gateways—to demonstrate the broad applicability of multi-threading in real-world applications.

Hardware multi-threading background

Multi-threading is a hardware- or software-based processing technique which has the primary objective of exploiting the concurrency in a computational workload to increase performance. Multi-threading can also be used to isolate various tasks so that priority can be assigned to more time-sensitive traffic such as voice, video or critical data. 

While software-based multi-threading techniques such as task switching and software-based thread scheduling are recognized to have been in existence for some time, less is known about the history of hardware based multi-threading.  Hardware-based multi-threading techniques have in fact existed for quite some time, with implementations dating back to the 1960s with the CDC6600 [1].  In the CDC6600 computer, 10 threads in hardware were used to guarantee response time from the I/O processor to the approximately 16 peripherals.  This example, where the processor ran much faster than the array of I/O devices, is a typical application which benefits greatly from multi-threading, as the idle processing time could be replaced with useful work in switching from thread to thread.  In the 1970s, the Denelcor HEP machine [2] switched on real execution threads within the CPU rather than on I/O.  Similar to the previous example, the net result was that instructions per cycle (IPC) were improved dramatically.  Several other systems and academic studies were introduced over the next decade that further demonstrated the benefits of hardware multithreading. 

Today there is an array of multi-threaded processors in the market.  Intel has brought a coarse grained version of the technology into the high-end computing application space with its Hyper-Threading technology.  Furthermore, numerous other SoC manufacturers such as Broadcom, Lantiq, Mobileye, Netlogic Microsystems, PMC-Sierra, Ralink Technology and Sigma Designs have also shipped millions of products with multi-threaded CPUs.  Many such SoCs are based on the multi-threaded MIPS32® 34K® core or the multi-threaded, multiprocessing MIPS32 1004K™ Coherent Processing System (CPS) based on the industry-standard MIPS® architecture.  Today, hardware multi-threading has reached mainstream adoption and is increasingly recognized as an efficient method for extracting optimal performance in SoC designs.

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