Achieving multicore performance in a single core SoC design using a multi-threaded virtual multiprocessor: Part 2
By Kevin D. Kissell and Pete Del Vecchio, MIPS Technologies
Nov 27 2006 (0:30 AM), Embedded.com
The key to the Virtual Processor Element (VPE) approach used in the MIPS 34K core is a set of extensions of the processor's basic instruction set architecture, rather than a specific set of hardware features to enable efficient multi-threading. In the case of the 34K core, the MT ASE is an application-specific extension of the MIPS32/MIPS64 instruction set and privileged resource architecture, meaning that it is a true architectural superset.
In the light of all this, the MIPS MT ASE strives to provide a framework both for the management of parallel threads on the same CPU and for the management of parallel threads across multiple cores, and indeed for the migration of threads from one multi-threaded processor to another.
To read the full article, click here
Related Semiconductor IP
- PUF FPGA-Xilinx Premium with key wrap
- ASIL-B Ready PUF Hardware Premium with key wrap and certification support
- ASIL-B Ready PUF Hardware Base
- PUF Software Premium with key wrap and certification support
- PUF Hardware Premium with key wrap and certification support
Related White Papers
- Internal JTAG - A cutting-edge solution for embedded instrument testing in SoC: Part 2
- SOC Stability in a Small Package
- Internal JTAG - A cutting-edge solution for embedded instrument testing in SoC: Part 1
- Integrating VESA DSC and MIPI DSI in a System-on-Chip (SoC): Addressing Design Challenges and Leveraging Arasan IP Portfolio
Latest White Papers
- e-GPU: An Open-Source and Configurable RISC-V Graphic Processing Unit for TinyAI Applications
- How to design secure SoCs, Part II: Key Management
- Seven Key Advantages of Implementing eFPGA with Soft IP vs. Hard IP
- Hardware vs. Software Implementation of Warp-Level Features in Vortex RISC-V GPU
- Data Movement Is the Energy Bottleneck of Today’s SoCs