Achieving multicore performance in a single core SoC design using a multi-threaded virtual multiprocessor: Part 2
By Kevin D. Kissell and Pete Del Vecchio, MIPS Technologies
Nov 27 2006 (0:30 AM), Embedded.com
The key to the Virtual Processor Element (VPE) approach used in the MIPS 34K core is a set of extensions of the processor's basic instruction set architecture, rather than a specific set of hardware features to enable efficient multi-threading. In the case of the 34K core, the MT ASE is an application-specific extension of the MIPS32/MIPS64 instruction set and privileged resource architecture, meaning that it is a true architectural superset.
In the light of all this, the MIPS MT ASE strives to provide a framework both for the management of parallel threads on the same CPU and for the management of parallel threads across multiple cores, and indeed for the migration of threads from one multi-threaded processor to another.
To read the full article, click here
Related Semiconductor IP
- UFS 5.0 Host Controller IP
- PDM Receiver/PDM-to-PCM Converter
- Voltage and Temperature Sensor with integrated ADC - GlobalFoundries® 22FDX®
- 8MHz / 40MHz Pierce Oscillator - X-FAB XT018-0.18µm
- UCIe RX Interface
Related Articles
- Integrating VESA DSC and MIPI DSI in a System-on-Chip (SoC): Addressing Design Challenges and Leveraging Arasan IP Portfolio
- ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design
- A RISC-V Multicore and GPU SoC Platform with a Qualifiable Software Stack for Safety Critical Systems
- Android hardware-software design using virtual prototypes - Part 2: Building a sensor subsystem
Latest Articles
- Enabling RISC-V Vector Code Generation in MLIR through Custom xDSL Lowerings
- A Scalable Open-Source QEC System with Sub-Microsecond Decoding-Feedback Latency
- SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks
- An FPGA Implementation of Displacement Vector Search for Intra Pattern Copy in JPEG XS
- A Persistent-State Dataflow Accelerator for Memory-Bound Linear Attention Decode on FPGA