The LEON3 processor is a synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 acrhitecture. The model is highly configurable, and particularly suitable for system-on-a-chip (SOC) designs. The full source code is available under the GNU GPL license, allowing free evaluation.
32-bit SPARC V8 processor
Overview
Key Features
- SPARC V8 compliant integer unit with 7-stage pipeline
- Hardware multiply, divide and MAC units
- Interface to FPU and custom co-processors
- Separate instruction and data cache (Hardvard architecture)
- Set-associative caches: 1 - 4 sets, 1 - 256 kbytes/set. Random, LRR or LRU replacement
- Data cache snooping
- On-chip 0-waitstate scratch pad RAM
- SPARC V8 reference memory management unit
- Power-down mode
- AMBA-2.0 AHB and APB on-chip buses
- Advanced on-chip debug support unit and trace buffer
- Includes synthesis and P&R scripts for several fpga boards
- Free GNU-based C Cross-compiler system
- Bsp's for RTEMS, eCos, Linux-2.5, uCLinux and VxWorks
Benefits
- Low cost license fee
- Easily prototyped on low-cost FPGA boards
- SPARC V8 conformant
- High performance (400 MHz 0.13 ASIC, 100 MHz FPGA)
- Low area (30 - 50 Kgates, 5 - 10,000 LUTs)
Deliverables
- Fully synthesisable VHDL code
- VHDL test bench
- Ducumentation
- Synthesis scripts
- Place&route scripts for FPGA boards
- GNU-based Cross-compiler
- High-performance behavioural simulator
- Technical support
Technical Specifications
Foundry, Node
Any
Maturity
Production
Availability
Immediate